Problems by Simulation with Virtuoso Analog Design Envirnome

[Andre]

Hallo,
I am new to this forum, and I am even new to by using Cadence. I have same problem with the Virtuoso Analog Design Envirnoment – tool.

I have installed the ic5.1.41, assura3.1.4, mmsim60, soc4.1, dsmse5.4 packet from Cadence and AMSv3.70 Design-Kit on Solaris 9.0.

After I started simulation with Virtuoso Analog Design Envirnoment CDS.log tells:

…
Compose simulator input file . . .
… successful.
Start stimulator if needed …
… successful.
Simuate. . .
Problems encountered during simulation.
Use the Simuation->Output Log menu for more information.

But there is no output.log. And I have no idea what is to do. I try to started the simulation with difference schematics und difference analyses. I get the same message every time: -Problems encountered during simulation.-

Has everyone an idea what is to do?

[hikom]

Hi,
please review the messages in CIW. In some cases the check&save was not executed --> simulation does not start. I hope this was the problem, if not post the messages in the CIW.
greetings,
hikom

[Andre]

Thanks for the help, but the Problem is another: check&save was successful!

I can no start the spectre simulator, that is the problem.
I am not sure, but I think I have forget something to do (after or during Installation). But I am not sure and Instalation was successful.

[hikom]

Hi,
so try to carry out a spectre simulation from the command line, typing spectre input.scs. If there is no error --> spectre is installed correct.
Greetings,
hikom