problems about hdl parser

[arsenal]

hi,
when i do mixed signal simulation in cadence, some problems occured.
i have compiled some digital .v files using verilog-xl 05.40.003-s, and it finished without errors.
and when i build a block in config and with the same code, the HDL parser give some errors at such codes as "wire signed", "20'sh00004" and "always @(*)",

so can anyone tell me what to do ?
thanks

[Andrew Beckett]

On Mon, 28 Nov 2005 19:10:08 -0600, dennishgj@yahoo-dot-com.no-spam.invalid
(arsenal) wrote:

hi,
when i do mixed signal simulation in cadence, some problems occured.
i have compiled some digital .v files using verilog-xl 05.40.003-s,
and it finished without errors.
and when i build a block in config and with the same code, the HDL
parser give some errors at such codes as "wire signed", "20'sh00004"
and "always @(*)",

so can anyone tell me what to do ?
thanks

You've not provided enough information for anyone to realistically be able to
help.

Andrew.

[arsenal]

thanks andrew,
i have written some codes in verilog and it passed compilation and can be synthesized, and the following statements are included,
wire signed [33:0] mydata;
assign mydata=34'h3f0000000;
assign mytest=(mydata == -34'sh010000000);
...

however,when i use the same codes in the behavioral view of a cell, which will be recompiled by HDL parser, errors were given in the above statements and marked as "syntax error", it seems HDL parser uses another version of verilog-xl and doesnt accept the syntax as "signed","sh"...

thanks a lot and urgent for your help.

arsenal

[Andrew Beckett]

On Tue, 29 Nov 2005 15:10:10 -0600, dennishgj@yahoo-dot-com.no-spam.invalid
(arsenal) wrote:

thanks andrew,
i have written some codes in verilog and it passed compilation and can
be synthesized, and the following statements are included,
wire signed [33:0] mydata;
assign mydata=34'h3f0000000;
assign mytest=(mydata == -34'sh010000000);
..

however,when i use the same codes in the behavioral view of a cell,
which will be recompiled by HDL parser, errors were given in the
above statements and marked as "syntax error", it seems HDL parser
uses another version of verilog-xl and doesnt accept the syntax as
"signed","sh"...

thanks a lot and urgent for your help.

arsenal

Ah, that's due to "van" being used to analyse the code. This is an old tool
which doesn't understand Verilog 2001 stuff.

If you set the following variable in your .cdsinit or in the CIW:

schHdlUseNcvlogForVerilog = t

Then it will use ncvlog instead (of course, you need to have ncvlog in the
path).

This is described in solution 11192234 on Sourcelink.

Regards,

Andrew.

[arsenal]

thank you very much Andrew,

i have done as you told me and now there is such a warning as:
ncvlog: *W,DLNOHV: Unable to find an 'hdl.var' file to load in.
will this warning matter?

and in my code, i includes more modules in one file, like following:

module a;
b #(3) b0(..);
b #(4) b1(..);
....
endmodule

module b;
parameter PB=1;
...
endmodule

and HDL parser just creates only one cell of b, and can it distinguish the different parameters?


thanks

arsenal

[Andrew Beckett]

On Wed, 30 Nov 2005 15:10:15 -0600, dennishgj@yahoo-dot-com.no-spam.invalid
(arsenal) wrote:

thank you very much Andrew,

i have done as you told me and now there is such a warning as:
ncvlog: *W,DLNOHV: Unable to find an 'hdl.var' file to load in.

and when i exit the hdl parser, it doesn't prompt me to create a
symbol for the cell.

thanks

arsenal

Haven't got time to check this now, but try creating an hdl.var file in the
working directory with the following contents:

SOFTINCLUDE $IUSHOME/tools/inca/files/hdl.var

where $IUSHOME is set to wherever your IUS installation is (can be whatever
env var you like, of course).

Andrew.