| Author |
Message |
Jal
Guest
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 Posted:
Tue Oct 05, 2004 12:36 pm Post subject:
Viewing multi-dimensional arrays in Simvision |
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[POSTED to .cad.cadence and .lang.verilog]
Hi,
Can somebody please inform me as to whether multi-dimensional arrays
are supported by NC-verilog and simvision.
I couldn't get NC-verilog to compile the following bit of code.
//4*4 array of byte
wire [7:0] my_array [1:0] [1:0];
So, instead, I used a 'reg', and this compiled OK,
//4*4 array of byte
reg [7:0] my_array [1:0] [1:0];
BUT, when I simulate my design, and open my .trn file in Simvision
(also tried signalscan), I can't seem to see any of my
multi-dimensional signals. I even tried a simple memory like this:
reg [7:0] mem [0:1023].
and even this was not displayed in the "signal/Variables of scope"
window.
Can these tools not display multi-dimensional arrays, or do I have to
set some kind of option somewhere?
p.s I am new to Verilog (ex-VHDL) and the Cadence toolset.
thanks,
Jal.
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John_H
Guest
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| Posted:
Tue Oct 05, 2004 8:04 pm Post subject:
Re: Viewing multi-dimensional arrays in Simvision |
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"Jal" <jalibahmed@hotmail.com> wrote in message
news:d8e046e.0410050036.3fbae8ee@posting.google.com...
| Quote: | [POSTED to .cad.cadence and .lang.verilog]
Hi,
Can somebody please inform me as to whether multi-dimensional arrays
are supported by NC-verilog and simvision.
|
[snip]
I don't have the experience with simvision, but I had a call in to the
Cadence folks about my 2-D wire troubles.
The array of nets construct
wire [7:0] MyWords [3:0];
is not supported in LDV51 or the current IUS53 release. The IUS54 release
due out sometime in November will provide the full support.
IUS53 - the first release after LDV51 - fixed my problems with conditional
generates and multi-dimensional part select (MyWords[1][1:0]) though bit
select (MyWords[1][2]) reportedly worked in LDV51. |
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Ajeetha Kumari
Guest
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| Posted:
Tue Oct 05, 2004 10:14 pm Post subject:
Re: Viewing multi-dimensional arrays in Simvision |
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Hi Jal,
Which version are you using? I used to use 5.1 and that supported
memory displays in waveform seamlessly, use the source browser to
locate the memory declaration and then you can send that memory to
waveform.
$CDS_INST_DIR/doc/simvision/displaying.html should have the needed
documentaion for it.
Regards,
Ajeetha
http://www.noveldv.com
jalibahmed@hotmail.com (Jal) wrote in message news:<d8e046e.0410050036.3fbae8ee@posting.google.com>...
| Quote: | [POSTED to .cad.cadence and .lang.verilog]
Hi,
Can somebody please inform me as to whether multi-dimensional arrays
are supported by NC-verilog and simvision.
I couldn't get NC-verilog to compile the following bit of code.
//4*4 array of byte
wire [7:0] my_array [1:0] [1:0];
So, instead, I used a 'reg', and this compiled OK,
//4*4 array of byte
reg [7:0] my_array [1:0] [1:0];
BUT, when I simulate my design, and open my .trn file in Simvision
(also tried signalscan), I can't seem to see any of my
multi-dimensional signals. I even tried a simple memory like this:
reg [7:0] mem [0:1023].
and even this was not displayed in the "signal/Variables of scope"
window.
Can these tools not display multi-dimensional arrays, or do I have to
set some kind of option somewhere?
p.s I am new to Verilog (ex-VHDL) and the Cadence toolset.
thanks,
Jal. |
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|
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Jal
Guest
|
| Posted:
Thu Oct 07, 2004 1:24 pm Post subject:
Re: Viewing multi-dimensional arrays in Simvision |
|
|
ajeetha@gmail.com (Ajeetha Kumari) wrote in message news:<de3cfe35.0410051014.404a203d@posting.google.com>...
| Quote: | Hi Jal,
Which version are you using? I used to use 5.1 and that supported
memory displays in waveform seamlessly, use the source browser to
locate the memory declaration and then you can send that memory to
waveform.
$CDS_INST_DIR/doc/simvision/displaying.html should have the needed
documentaion for it.
Regards,
Ajeetha
http://www.noveldv.com
jalibahmed@hotmail.com (Jal) wrote in message news:<d8e046e.0410050036.3fbae8ee@posting.google.com>...
[POSTED to .cad.cadence and .lang.verilog]
Hi,
Can somebody please inform me as to whether multi-dimensional arrays
are supported by NC-verilog and simvision.
I couldn't get NC-verilog to compile the following bit of code.
//4*4 array of byte
wire [7:0] my_array [1:0] [1:0];
So, instead, I used a 'reg', and this compiled OK,
//4*4 array of byte
reg [7:0] my_array [1:0] [1:0];
BUT, when I simulate my design, and open my .trn file in Simvision
(also tried signalscan), I can't seem to see any of my
multi-dimensional signals. I even tried a simple memory like this:
reg [7:0] mem [0:1023].
and even this was not displayed in the "signal/Variables of scope"
window.
Can these tools not display multi-dimensional arrays, or do I have to
set some kind of option somewhere?
p.s I am new to Verilog (ex-VHDL) and the Cadence toolset.
thanks,
Jal.
|
Hi,
The problem seemed to be the way I was using the $shm_probe task.
My original code looked like this:
$shm_probe("AC");
This only allows signals and wires to be probed, and therefore all
memories are left out, and consequently will not appear in the wave
window.
Changing the code to:
$shm_probe(tb_top, ("AC"), tb_top.DUT("AM"));
where 'tb_top' is the top level module (my testfixture), and
'tb_top.DUT' is where my memory is declared.
This fixed the problem, as memories (i.e multi-dim arrays) are also
probed during simulation.
regards
Jal. |
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