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Manuel Koch · Guest

Hi,
I have the following problem:

I created several layout cells, each of them has its own supply lines.
In these cells I attach symbolic pins to the supply lines,
so e.g. the DRC knows that an n-well is no longer 'hot' because it is
connected to vdd!
LVS works fine in these cells.

Later I assemble several cells on a higher level of hierarchy, the
problem now is that
the previously defined pins have no effect on this hierarchy level.
That results e.g. in DRC errors because
every n-well is now 'hot' again; when I do extract/LVS nets with same
name are not joined (even if i turn on that option during extract).

My workaround up to now:
I place new pins in every new hierarchy level right on top of the pins
that are already in the cells.
This works fine, but results in a lot of work and if e.g. I have to
change a terminal name it gets quite horrible.

Do you have any suggestions how to better handle such a scenario?
How do you do such a bottom-up design with continuous LVS checking?

kind regards,

Manuel Koch

Diva Physical Verificatio · Guest

This is the normal way hierarchical design with bottom up LVS is done.
You ARE over-doing the pins in each level if you are putting them on top
of every pin in the child cells. The child cell pins should be connected
together and pins added for the new cell's interface to the next level
of hierarchy. That should mean only one VDD and one GND pin, plus the
IOs for the new cell.

The reason the child cell pins are ignored is because they are local to
the child cell. Each instance of the child cell can potentially be
connected to a different net, so the child cell pins cannot be promoted
to the parent cell without creating unexpected connections. In your
case, that promotion might work as you intend, but in the general case,
it will not.

As a side note, you should never use the option to join nets with the
same name unless you very specifically designed your cell to have two
pins that must be connected externally.

On 7 Oct 2004 09:12:17 -0700, makoc@gmx.de (Manuel Koch) wrote:

Manuel Koch · Guest

Diva Physical Verification <diva@cadence.com> wrote in message news:<0pcbm01pe1i3c997rt3kj6fqoid1mkil76@4ax.com>...

Diva Physical Verificatio · Guest

Unless the child cells are stand-alone blocks that do not interact with
any other cells, they have to be able to be connected together. If you
cannot connect them in the layout, they will not be connected on the
die.

On 7 Oct 2004 23:16:20 -0700, makoc@gmx.de (Manuel Koch) wrote:

Manuel Koch · Guest

Diva Physical Verificatio · Guest

Yes. The hierarchy should be defined to facilitate that, grouping blocks
that form a higher level block. If you match your schematic hierarchy
and layout hierarchy, you can get creative and use macrocell extraction
to feed LVS functional netlists instead of transistor netlists and
verify your entire design, from the bottom up, as you go. Without having
to switch to another tool when the design becomes large. I have heard of
a customer doing a 50 million transistor design, using only Diva DRC and
LVS, that way. It takes discipline, though.

On 9 Oct 2004 03:15:34 -0700, makoc@gmx.de (Manuel Koch) wrote:

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