| Author |
Message |
fogh
Guest
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 Posted:
Thu Sep 16, 2004 4:52 pm Post subject:
random bitstream generator. |
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Hi All,
I found the random bitstream generator in ahdlLib (category telecom) to be not-so-random, and even obviously periodic with a big bad DC offset from eqiprobability. This is with spectre from IC446.100.92, and the verilogA in IC446 is the same as in IC5.
I came up with the following in an attempt to fix it, but I am new to verilogAMS, so please review it. I know that handling of zero rise time or fall time could be better, but I would rather the CDF callbacks deal with this. (BTW: when, oh when, will those ahdlLib symbol be deuglyfied ? )
//--------------------
// rand_bit_stream
//
// - Random bit steam generator
//
// vout: [V,A]
//
// INSTANCE parameters
// tperiod = period of stream [s]
// seed = random number seed []
// vlogic_high = output voltage for high [V]
// vlogic_low = output voltage for low [V]
// tdel, trise, tfall = {usual} [s]
//
// MODEL parameters
// {none}
//
// This model generates a random steam of bits.
//
module rand_bit_stream (vout);
output vout;
electrical vout;
parameter real tperiod = 1n from (0:inf);
parameter integer seed = 0;
parameter real vlogic_high = 2.2;
parameter real vlogic_low = 0 ;
parameter real tdel=0 from [0:inf);
parameter real trise=10p from (0:inf);
parameter real tfall=50p from (0:inf);
real next, vout_val, mintime,transition_accuracy;
integer bit;
analog begin
$bound_step(tperiod); //ensure the simulator will not step over
@ ( initial_step ) begin
next = $abstime + tperiod;
mintime=min(min(abs(trise),abs(tfall)),abs(tperiod));
//mintime=mintime+0.1f;
transition_accuracy=1m; //this is dimensionless.
bit = $random(seed) & 1;
vout_val = (vlogic_high - vlogic_low) * bit + vlogic_low;
end
//bit = abs($random) & 1;
bit = $random & 1;
@ ( timer( next )) begin
vout_val = (vlogic_high - vlogic_low) * bit + vlogic_low;
next = next + tperiod;
if(mintime>0) $bound_step(mintime);
$discontinuity (1); //announce discontinuity of first derivative
end
// V(vout) <+ transition(vout_val,tdel,trise,tfall,mintime*transition_accuracy); //not accepted yet by spectre446.
V(vout) <+ transition(vout_val,tdel,trise,tfall);
end //analog
endmodule
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fogh
Guest
|
| Posted:
Thu Sep 16, 2004 9:14 pm Post subject:
Re: random bitstream generator. |
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//--------------------
// rand_bit_stream
//
// - Random bit steam generator
//
// vout: [V,A]
//
// INSTANCE parameters
// tperiod = period of stream [s]
// seed = random number seed []
// vlogic_high = output voltage for high [V]
// vlogic_low = output voltage for low [V]
// tdel, trise, tfall = {usual} [s]
//
// MODEL parameters
// {none}
//
// This model generates a random steam of bits.
//
module rand_bit_stream (vout);
output vout;
electrical vout;
parameter real tperiod = 1n from (0:inf);
parameter integer seed = 0;
parameter real vlogic_high = 2.2;
parameter real vlogic_low = 0 ;
parameter real tdel=0 from [0:inf);
parameter real trise=10p from (0:inf);
parameter real tfall=50p from (0:inf);
real next, vout_val, mintime,transition_accuracy;
integer bit;
analog begin
$bound_step(tperiod); //ensure the simulator will not step over
@ ( initial_step ) begin
next = $abstime + tperiod;
mintime=min(min(abs(trise),abs(tfall)),abs(tperiod));
transition_accuracy=1m; //this is dimensionless.
bit = $random(seed) & 1;
end
@ ( timer( next )) begin
bit = $random & 1;
next = next + tperiod;
if(mintime>0) $bound_step(mintime);
$discontinuity(1); //announce discontinuity of first derivative
end
vout_val = bit?vlogic_high:vlogic_low;
V(vout) <+ transition(vout_val,tdel,trise,tfall);
// V(vout) <+ transition(vout_val,tdel,trise,tfall,mintime*transition_accuracy); //not accepted yet by spectre446.
end //analog
endmodule
fogh wrote:
| Quote: | Hi All,
I found the random bitstream generator in ahdlLib (category telecom) to
be not-so-random, and even obviously periodic with a big bad DC offset
from eqiprobability. This is with spectre from IC446.100.92, and the
verilogA in IC446 is the same as in IC5.
I came up with the following in an attempt to fix it, but I am new to
verilogAMS, so please review it. I know that handling of zero rise time
or fall time could be better, but I would rather the CDF callbacks deal
with this. (BTW: when, oh when, will those ahdlLib symbol be deuglyfied ? )
//--------------------
// rand_bit_stream
//
// - Random bit steam generator
//
// vout: [V,A]
//
// INSTANCE parameters
// tperiod = period of stream [s]
// seed = random number seed []
// vlogic_high = output voltage for high [V]
// vlogic_low = output voltage for low [V]
// tdel, trise, tfall = {usual} [s]
//
// MODEL parameters
// {none}
//
// This model generates a random steam of bits.
//
module rand_bit_stream (vout);
output vout;
electrical vout;
parameter real tperiod = 1n from (0:inf);
parameter integer seed = 0;
parameter real vlogic_high = 2.2;
parameter real vlogic_low = 0 ;
parameter real tdel=0 from [0:inf);
parameter real trise=10p from (0:inf);
parameter real tfall=50p from (0:inf);
real next, vout_val, mintime,transition_accuracy;
integer bit;
analog begin
$bound_step(tperiod); //ensure the simulator will not step over
@ ( initial_step ) begin
next = $abstime + tperiod;
mintime=min(min(abs(trise),abs(tfall)),abs(tperiod));
//mintime=mintime+0.1f;
transition_accuracy=1m; //this is dimensionless.
bit = $random(seed) & 1;
vout_val = (vlogic_high - vlogic_low) * bit + vlogic_low;
end
//bit = abs($random) & 1;
bit = $random & 1;
@ ( timer( next )) begin
vout_val = (vlogic_high - vlogic_low) * bit + vlogic_low;
next = next + tperiod;
if(mintime>0) $bound_step(mintime);
$discontinuity (1); //announce discontinuity of first derivative
end
// V(vout) <+
transition(vout_val,tdel,trise,tfall,mintime*transition_accuracy); //not
accepted yet by spectre446.
V(vout) <+ transition(vout_val,tdel,trise,tfall);
end //analog
endmodule
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fogh
Guest
|
| Posted:
Wed Sep 22, 2004 2:35 pm Post subject:
math check on the DFT (Re: random bitstream generator.) |
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|
What spectrum should I expect when randomness is good ? (for instance with tperiod=vlogic_high=1 vlogic_low=-1, trise=tfall=1m, 10**5 cycles )?
fogh wrote:
| Quote: | //--------------------
// rand_bit_stream
//
// - Random bit steam generator
//
// vout: [V,A]
//
// INSTANCE parameters
// tperiod = period of stream [s]
// seed = random number seed []
// vlogic_high = output voltage for high [V]
// vlogic_low = output voltage for low [V]
// tdel, trise, tfall = {usual} [s]
//
// MODEL parameters
// {none}
//
// This model generates a random steam of bits.
//
module rand_bit_stream (vout);
output vout;
electrical vout;
parameter real tperiod = 1n from (0:inf);
parameter integer seed = 0;
parameter real vlogic_high = 2.2;
parameter real vlogic_low = 0 ;
parameter real tdel=0 from [0:inf);
parameter real trise=10p from (0:inf);
parameter real tfall=50p from (0:inf);
real next, vout_val, mintime,transition_accuracy;
integer bit;
analog begin
$bound_step(tperiod); //ensure the simulator will not step over
@ ( initial_step ) begin
next = $abstime + tperiod;
mintime=min(min(abs(trise),abs(tfall)),abs(tperiod));
transition_accuracy=1m; //this is dimensionless.
bit = $random(seed) & 1;
end
@ ( timer( next )) begin
bit = $random & 1;
next = next + tperiod;
if(mintime>0) $bound_step(mintime);
$discontinuity(1); //announce discontinuity of first derivative
end
vout_val = bit?vlogic_high:vlogic_low;
V(vout) <+ transition(vout_val,tdel,trise,tfall);
// V(vout) <+
transition(vout_val,tdel,trise,tfall,mintime*transition_accuracy); //not
accepted yet by spectre446.
end //analog
endmodule
fogh wrote:
Hi All,
I found the random bitstream generator in ahdlLib (category telecom)
to be not-so-random, and even obviously periodic with a big bad DC
offset from eqiprobability. This is with spectre from IC446.100.92,
and the verilogA in IC446 is the same as in IC5.
I came up with the following in an attempt to fix it, but I am new to
verilogAMS, so please review it. I know that handling of zero rise
time or fall time could be better, but I would rather the CDF
callbacks deal with this. (BTW: when, oh when, will those ahdlLib
symbol be deuglyfied ? )
//--------------------
// rand_bit_stream
//
// - Random bit steam generator
//
// vout: [V,A]
//
// INSTANCE parameters
// tperiod = period of stream [s]
// seed = random number seed []
// vlogic_high = output voltage for high [V]
// vlogic_low = output voltage for low [V]
// tdel, trise, tfall = {usual} [s]
//
// MODEL parameters
// {none}
//
// This model generates a random steam of bits.
//
module rand_bit_stream (vout);
output vout;
electrical vout;
parameter real tperiod = 1n from (0:inf);
parameter integer seed = 0;
parameter real vlogic_high = 2.2;
parameter real vlogic_low = 0 ;
parameter real tdel=0 from [0:inf);
parameter real trise=10p from (0:inf);
parameter real tfall=50p from (0:inf);
real next, vout_val, mintime,transition_accuracy;
integer bit;
analog begin
$bound_step(tperiod); //ensure the simulator will not step over
@ ( initial_step ) begin
next = $abstime + tperiod;
mintime=min(min(abs(trise),abs(tfall)),abs(tperiod));
//mintime=mintime+0.1f;
transition_accuracy=1m; //this is dimensionless.
bit = $random(seed) & 1;
vout_val = (vlogic_high - vlogic_low) * bit + vlogic_low;
end
//bit = abs($random) & 1;
bit = $random & 1;
@ ( timer( next )) begin
vout_val = (vlogic_high - vlogic_low) * bit + vlogic_low;
next = next + tperiod;
if(mintime>0) $bound_step(mintime);
$discontinuity (1); //announce discontinuity of first derivative
end
// V(vout) <+
transition(vout_val,tdel,trise,tfall,mintime*transition_accuracy);
//not accepted yet by spectre446.
V(vout) <+ transition(vout_val,tdel,trise,tfall);
end //analog
endmodule
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Stefan Joeres
Guest
|
| Posted:
Wed Sep 22, 2004 7:55 pm Post subject:
Re: math check on the DFT (Re: random bitstream generator.) |
|
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fogh wrote:
| Quote: |
What spectrum should I expect when randomness is good ? (for instance with
tperiod=vlogic_high=1 vlogic_low=-1, trise=tfall=1m, 10**5 cycles )?
|
As far as I remember _real_ random bit streams produce a flat spectrum
(white noise). This is just true for a very long period, so if you watch
over a shorter period of time, you should get a nearly flat spectrum with
two blops somewhere which are produced by the sharp transititions and the
flat plateau.
Sincerely,
Stefan
--
Dipl.-Ing. Stefan Joeres
Lehrstuhl für Integrierte Analogschaltungen
RWTH Aachen
Sommerfeldstr. 24
D-52074 Aachen
Tel: +49-241-8027752 (office)
Fax: +49-241-8022199 |
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fogh
Guest
|
| Posted:
Fri Sep 24, 2004 2:54 am Post subject:
Re: math check on the DFT (Re: random bitstream generator.) |
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|
Stefan Joeres wrote:
| Quote: | fogh wrote:
What spectrum should I expect when randomness is good ? (for instance with
tperiod=vlogic_high=1 vlogic_low=-1, trise=tfall=1m, 10**5 cycles )?
As far as I remember _real_ random bit streams produce a flat spectrum
(white noise). This is just true for a very long period, so if you watch
over a shorter period of time, you should get a nearly flat spectrum with
two blops somewhere which are produced by the sharp transititions and the
flat plateau.
Stefan, |
that is what I expected too, but I get stg that looks more like a
sinc. It is flat at higher freqs, but that could be a numerical noise
floor. Is there a way to get the spectrum from autocorrelation
considerations ?
(sorry for any stupid signal processing question. My standard excuse is
: Sorry but I studied only physics. I wanted to major in blond bodies
but dropped out and had to do semiconductors.)
No, honestly, if someone can check the verilogA code or the spectrum, I
would appreciate. |
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fogh
Guest
|
| Posted:
Mon Sep 27, 2004 8:43 pm Post subject:
Re: math check on the DFT (Re: random bitstream generator.) |
|
|
fogh wrote:
| Quote: | Stefan Joeres wrote:
fogh wrote:
What spectrum should I expect when randomness is good ? (for instance
with
tperiod=vlogic_high=1 vlogic_low=-1, trise=tfall=1m, 10**5 cycles )?
As far as I remember _real_ random bit streams produce a flat spectrum
(white noise). This is just true for a very long period, so if you
watch over a shorter period of time, you should get a nearly flat
spectrum with two blops somewhere which are produced by the sharp
transititions and the flat plateau.
Stefan,
that is what I expected too, but I get stg that looks more like a sinc.
It is flat at higher freqs, but that could be a numerical noise floor.
Is there a way to get the spectrum from autocorrelation considerations ?
(sorry for any stupid signal processing question. My standard excuse is
: Sorry but I studied only physics. I wanted to major in blond bodies
but dropped out and had to do semiconductors.)
No, honestly, if someone can check the verilogA code or the spectrum, I
would appreciate.
|
Hi All,
I got the spectrum now. There are 2 ways to get at it:
1) the autocorrelation
With this rndbs(t) function, the autocorrelation R(d) is the average of rndbs(t)*rndbs(t-d) . When you are still on the same bit, the correlation is complete, but if you look after 1 period (1 second) than there is no correlation at all. That is, when |d|<0.5 we have R=1 and for |d|>0.5 we have R=0.
Some theorem tells us that the spectrum F(s) is the fourier tranform of R(d) . That's the transform of a door, so the spectrum is a sin(s)/s
2) the convolution
If you take in your DFT only one sample per clock, you have a "random train of diracs" rtd(t). Like Stefan said, the spectrum of this guy is flat.
If you convolute this random train with a door function, you get the actual waveform generated in time domain by the verilogA module.
The Fourier tranform of a convolution is the product of the tranforms = flat() * tranform(door()) = tranform(door())= sin(s)/s |
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