Ben
Guest
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 Posted:
Fri Nov 25, 2005 5:10 pm Post subject:
veriloga -> loop of rigid brqnches (shorts) |
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I would realise a polarisation stage in veriloga language.
I need to instantiate 80 similar polarisations stages (PolaStage<79:0>).
Each stage has the same input current (in) but not the same output
voltage (out<79:0>).
So if I have a current source of 80ľA, each stage see only 1ľA.
To simplify my problem, I wrote :
| Quote: |
branch (in,gnd) toto
analog begin
outval = K * I(toto);
V(out) <+ outval;
end
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the parser didn't see error but when I start spectre, I have a fatal error :
The following branches form a loop of rigid branches (shorts) when added
to the circuit :
PolaStage_0:in_flow (from in to 0)
PolaStage_1:in_flow (from in to 0)
PolaStage_2:in_flow (from in to 0)
PolaStage_3:in_flow (from in to 0)
.....
Is it really impossible to write a veriloga close to the schematic in
this case ??
Thanks for your help
Ben
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Andrew Beckett
Guest
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| Posted:
Mon Nov 28, 2005 1:10 pm Post subject:
Re: veriloga -> loop of rigid brqnches (shorts) |
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On Fri, 25 Nov 2005 15:49:54 +0100, Ben <ben138306@yahoo.fr> wrote:
| Quote: | I would realise a polarisation stage in veriloga language.
I need to instantiate 80 similar polarisations stages (PolaStage<79:0>).
Each stage has the same input current (in) but not the same output
voltage (out<79:0>).
So if I have a current source of 80ľA, each stage see only 1ľA.
To simplify my problem, I wrote :
branch (in,gnd) toto
analog begin
outval = K * I(toto);
V(out) <+ outval;
end
the parser didn't see error but when I start spectre, I have a fatal error :
The following branches form a loop of rigid branches (shorts) when added
to the circuit :
PolaStage_0:in_flow (from in to 0)
PolaStage_1:in_flow (from in to 0)
PolaStage_2:in_flow (from in to 0)
PolaStage_3:in_flow (from in to 0)
....
Is it really impossible to write a veriloga close to the schematic in
this case ??
Thanks for your help
Ben
|
To avoid re-saying the same thing, I answered this at:
http://www.designers-guide.org/Forum/?board=verilogams;action=display;num=1132929989
Andrew. |
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