| Author |
Message |
PK
Guest
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 Posted:
Mon Nov 14, 2005 1:10 pm Post subject:
creating global nets in analog design environment |
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Hi,
I am trying to create a global net in the 'analog design environment'
or in the virtuoso schematic editor. I would like to create a global
net called _net0
The only global net symbols I find in analogLib or basic are for
vdd-like, vss-like or gnd-like nets. I do not find a symbol that allows
me to choose my own name.
In the analog design environment I did not succeed in specifying global
nets. There does not seem to be a place to do it.
The only work around I have now is in ADE to create the netlist ->
manually edit the input.scs -> do Simulation -> Run in ADE. I also
tried to change in the netlistHeader in the netlist directory. However,
that gets overwritten everytime a schematic is created. It does have a
"global 0" statement though.
This problem originates from simulating an extracted netlist. The
substrate node is extracted as _net0 . At this point changing the
extraction is not an option.
Thanks,
PK
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Bernd Fischer
Guest
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| Posted:
Mon Nov 14, 2005 1:10 pm Post subject:
Re: creating global nets in analog design environment |
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You simply create a global net by putting an exclamation mark
direct after the net name 'netName!'.
Think it's also worth to have a look for inherited connections in
the documentation.
Bernd
PK wrote:
| Quote: | Hi,
I am trying to create a global net in the 'analog design environment'
or in the virtuoso schematic editor. I would like to create a global
net called _net0
The only global net symbols I find in analogLib or basic are for
vdd-like, vss-like or gnd-like nets. I do not find a symbol that allows
me to choose my own name.
In the analog design environment I did not succeed in specifying global
nets. There does not seem to be a place to do it.
The only work around I have now is in ADE to create the netlist -
manually edit the input.scs -> do Simulation -> Run in ADE. I also
tried to change in the netlistHeader in the netlist directory. However,
that gets overwritten everytime a schematic is created. It does have a
"global 0" statement though.
This problem originates from simulating an extracted netlist. The
substrate node is extracted as _net0 . At this point changing the
extraction is not an option.
Thanks,
PK
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fogh
Guest
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| Posted:
Mon Nov 14, 2005 9:10 pm Post subject:
Re: creating global nets in analog design environment |
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PK wrote:
| Quote: | Thanks for your reply. I forgot to mention that I need the global net
to be called _net0 and not something else. I know that I could make
_net0! global. I am starting from an extracted circuit description that
is using the _net0 node and it is not included in the subckt interface
definition. So I am trying to connect to it by making _net0 global.
In netlist a global will always (traditionally) have a bang ! |
If you want to alter the "global" statement made by spectre netlister,
your would have to work on the spectre-direct ADE flowchart or
netlisters. Not worth the trouble, is it ?
Just use any good old text utility and put a bang in the netlist.
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PK
Guest
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| Posted:
Mon Nov 14, 2005 9:10 pm Post subject:
Re: creating global nets in analog design environment |
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Thanks for your reply. I forgot to mention that I need the global net
to be called _net0 and not something else. I know that I could make
_net0! global. I am starting from an extracted circuit description that
is using the _net0 node and it is not included in the subckt interface
definition. So I am trying to connect to it by making _net0 global.
Thanks,
-- PK |
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PK
Guest
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| Posted:
Wed Nov 16, 2005 1:10 pm Post subject:
Re: creating global nets in analog design environment |
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fogh wrote:
| Quote: | PK wrote:
Thanks for your reply. I forgot to mention that I need the global net
to be called _net0 and not something else. I know that I could make
_net0! global. I am starting from an extracted circuit description that
is using the _net0 node and it is not included in the subckt interface
definition. So I am trying to connect to it by making _net0 global.
In netlist a global will always (traditionally) have a bang !
If you want to alter the "global" statement made by spectre netlister,
your would have to work on the spectre-direct ADE flowchart or
netlisters. Not worth the trouble, is it ?
Just use any good old text utility and put a bang in the netlist.
|
Sure, still it is disappointing that such a simple task would require
going into the netlisting setup or requires a manual intervention. The
problem with the manual/editor approach is that everytime the netlister
does a full netlist based on the extracted views, you have to repeat
your manual/editing. But it works.
Thanks for the pointers.
-- PK |
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fogh
Guest
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| Posted:
Thu Nov 17, 2005 9:10 pm Post subject:
Re: creating global nets in analog design environment |
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PK wrote:
| Quote: | fogh wrote:
PK wrote:
Thanks for your reply. I forgot to mention that I need the global net
to be called _net0 and not something else. I know that I could make
_net0! global. I am starting from an extracted circuit description that
is using the _net0 node and it is not included in the subckt interface
definition. So I am trying to connect to it by making _net0 global.
In netlist a global will always (traditionally) have a bang !
If you want to alter the "global" statement made by spectre netlister,
your would have to work on the spectre-direct ADE flowchart or
netlisters. Not worth the trouble, is it ?
Just use any good old text utility and put a bang in the netlist.
Sure, still it is disappointing that such a simple task would require
going into the netlisting setup or requires a manual intervention. The
problem with the manual/editor approach is that everytime the netlister
does a full netlist based on the extracted views, you have to repeat
your manual/editing. But it works.
|
What you would need rather a global is to access the net with its
hierarchical name like "I0._net0"
I don t know of such feature in composer or spectre though. |
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Andrew Beckett
Guest
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| Posted:
Fri Nov 18, 2005 9:10 am Post subject:
Re: creating global nets in analog design environment |
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On Thu, 17 Nov 2005 21:59:12 -0500, fogh <adff@xs4all.nl> wrote:
| Quote: | PK wrote:
fogh wrote:
PK wrote:
Thanks for your reply. I forgot to mention that I need the global net
to be called _net0 and not something else. I know that I could make
_net0! global. I am starting from an extracted circuit description that
is using the _net0 node and it is not included in the subckt interface
definition. So I am trying to connect to it by making _net0 global.
In netlist a global will always (traditionally) have a bang !
If you want to alter the "global" statement made by spectre netlister,
your would have to work on the spectre-direct ADE flowchart or
netlisters. Not worth the trouble, is it ?
Just use any good old text utility and put a bang in the netlist.
Sure, still it is disappointing that such a simple task would require
going into the netlisting setup or requires a manual intervention. The
problem with the manual/editor approach is that everytime the netlister
does a full netlist based on the extracted views, you have to repeat
your manual/editing. But it works.
What you would need rather a global is to access the net with its
hierarchical name like "I0._net0"
I don t know of such feature in composer or spectre though.
|
I wrote solution for sourcelink last year which allows you to do this:
11017972 - Creating a component which allows probing down through hierarchy
This only works for spectre, but you can place a component on the schematic with
a hierarchical reference to a net - and then you can make a connection in your
top level testbench to that internal net of a lower block - so you could tie it
to whereever you need to. This would avoid you having to edit the netlist
you're including.
Search for that solution number on sourcelink.cadence.com and you'll find it. It
has an attachment with the component - which is mostly taken care of by a
custom netlisting procedure.
Best Regards,
Andrew. |
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