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Saran · Guest

Hi,

I am just starting to gain experience on cadence tools. I am trying to
do a simulation using analog environment. This is a simple flip flop
written in verilog. I have imported that to schematic and then using
spectreverilog in analog enviroment. I am getting the following error
when I netlist and run the simulation...Can anyone guide me in the
right direction..

Thanks a lot

Regs,
Saran
____

Simulating `analog/input.scs' on vlsi32 at 2:56:46 PM, Sun Nov 7,
2004.

Error found by spectre during circuit read-in.
"analog/input.scs" 26: Syntax error in specification of
`_ie99997'.

spectre terminated prematurely due to fatal error.

----

Andrew Beckett · Guest

Can you share that part of the netlist?

It's virtually impossible to tell without seeing more detail. Nothing
in your description gives any clue as to why this should happen,
because you don't appear to be doing anything out of the ordinary.

Regards,

Andrew.

On 7 Nov 2004 11:58:30 -0800, saranyan13@gmail.com (Saran) wrote:

Saran · Guest

Hi Andrew,

Here is the netlist...i am getting the error
Simulating `analog/input.scs' on vlsi32 at 1:53:39 PM, Tue Nov 9,
2004.

Error found by spectre during circuit read-in.
"analog/input.scs" 29: Syntax error in specification of
`_ie99998'.

spectre terminated prematurely due to fatal error.
___

Thanks once again...
I am virutally stuck here..Not getting myself moving in the proper
direction. Any help would be greatly appreciated.

Netlist
___

// Generated for: spectre
// Generated on: Nov 9 13:34:27 2004
// Design library name: Saran_MS_Tut
// Design cell name: AOI_test
// Design view name: config
simulator lang=spectre
global 0
include "/usr/local/cadence/ic5141/tools.sun4v/dfII/samples/artist/ahdlLib/quantity.spectre"
include "/usr/local/NCSU_CDK.1.2/local/models/spectre/standalone/ami16N.m"
include "/usr/local/NCSU_CDK.1.2/local/models/spectre/standalone/ami16P.m"
// BEGIN Flat Interface Elements
// Flattened IE at /net5 uses port path 99999
// Flattened IE at /net11 uses port path 99998
// Flattened IE at /net7 uses port path 99997
// END Flat Interface Elements

// Library name: Saran_MS_Tut
// Cell name: AOI_test
// View name: schematic
// Inherited view list: spectre spice verilog behavioral functional
hdl
//system verilogNetlist schematic cmos.sch cmos_sch veriloga ahdl
V2 (net11 net4) vsource dc=0 type=dc
C0 (net4 0) capacitor c=10f
V1 (net5 0) vsource type=pulse val0=1 val1=5 width=20n
V0 (net7 0) vsource type=pulse val0=1 val1=5 width=10n
// BEGIN Hierarchical Interface Elements
_ie99997 (net7 0) a2d dest="99997" timex=1m vl=1.5 vh=3.5
_ie99998 (net11 0) d2a src="99998" fall=2n rise=3n val1=5 val0=0 valx=
\
valz=
_ie99999 (net5 0) a2d dest="99999" timex=1m vl=1.5 vh=3.5
// END Hierarchical Interface Elements
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12
temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5
maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \
sensfile="../psf/sens.output"
tran tran stop=200m write="spectre.ic" writefinal="spectre.fc" \
annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
save V2:p
saveOptions options save=allpub
___

Saran · Guest

This is a repost...I am sorry...The last post for some reason was not
being displayed

Hi Andrew,

Here is the netlist...i am getting the error
Simulating `analog/input.scs' on vlsi32 at 1:53:39 PM, Tue Nov 9,
2004.

Error found by spectre during circuit read-in.
"analog/input.scs" 29: Syntax error in specification of
`_ie99998'.

spectre terminated prematurely due to fatal error.
___

Thanks once again...
I am virutally stuck here..Not getting myself moving in the proper
direction. Any help would be greatly appreciated.

Netlist
___

// Generated for: spectre
// Generated on: Nov 9 13:34:27 2004
// Design library name: Saran_MS_Tut
// Design cell name: AOI_test
// Design view name: config
simulator lang=spectre
global 0
include "/usr/local/cadence/ic5141/tools.sun4v/dfII/samples/artist/ahdlLib/quantity.spectre"
include "/usr/local/NCSU_CDK.1.2/local/models/spectre/standalone/ami16N.m"
include "/usr/local/NCSU_CDK.1.2/local/models/spectre/standalone/ami16P.m"
// BEGIN Flat Interface Elements
// Flattened IE at /net5 uses port path 99999
// Flattened IE at /net11 uses port path 99998
// Flattened IE at /net7 uses port path 99997
// END Flat Interface Elements

// Library name: Saran_MS_Tut
// Cell name: AOI_test
// View name: schematic
// Inherited view list: spectre spice verilog behavioral functional
hdl
//system verilogNetlist schematic cmos.sch cmos_sch veriloga ahdl
V2 (net11 net4) vsource dc=0 type=dc
C0 (net4 0) capacitor c=10f
V1 (net5 0) vsource type=pulse val0=1 val1=5 width=20n
V0 (net7 0) vsource type=pulse val0=1 val1=5 width=10n
// BEGIN Hierarchical Interface Elements
_ie99997 (net7 0) a2d dest="99997" timex=1m vl=1.5 vh=3.5
_ie99998 (net11 0) d2a src="99998" fall=2n rise=3n val1=5 val0=0 valx=
\
valz=
_ie99999 (net5 0) a2d dest="99999" timex=1m vl=1.5 vh=3.5
// END Hierarchical Interface Elements
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12
temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5
maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \
sensfile="../psf/sens.output"
tran tran stop=200m write="spectre.ic" writefinal="spectre.fc" \
annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
save V2:p
saveOptions options save=allpub
___

Saran · Guest

I figured out the problem...Thanks.

Basically in the schematic, in the mixed signal menu, two interface
elements of the library were not specified. I had to specify them to
get it working. Everything works fine now. Thanks a lot for taking
time to suggest solutions to this problem.

Saran

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