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Message |
Jay Smith
Guest
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 Posted:
Fri Sep 03, 2004 9:38 am Post subject:
Assura LVS questions: layout and schematic match but got an |
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Greetings,
I did a couple of Assura LVS checks lately. All of my layouts match
the schematics. However, among them, I got some "error messages" from
within the ELW. Seems these errors won't affect RCX run, but what
exactly do these messages (from the ELW) mean?
------------------------------------------------
nxwell_StampErrorMult
nxwell_StampErrorConnect
psub_term_StampErrorMult
psub_term_StampErrorConnect
psub_StampErrorMult
psub_StampErrorConnect
------------------------------------------------
Thanks a lot for your inputs!
Jay
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Diva Physical Verificatio
Guest
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| Posted:
Fri Sep 03, 2004 11:08 am Post subject:
Re: Assura LVS questions: layout and schematic match but got |
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Just off hand, I'd say you have not tied your substrate and wells to
power properly.
On 2 Sep 2004 22:38:47 -0700, mail9900@yahoo.com (Jay Smith) wrote:
| Quote: | Greetings,
I did a couple of Assura LVS checks lately. All of my layouts match
the schematics. However, among them, I got some "error messages" from
within the ELW. Seems these errors won't affect RCX run, but what
exactly do these messages (from the ELW) mean?
------------------------------------------------
nxwell_StampErrorMult
nxwell_StampErrorConnect
psub_term_StampErrorMult
psub_term_StampErrorConnect
psub_StampErrorMult
psub_StampErrorConnect
------------------------------------------------
Thanks a lot for your inputs!
Jay |
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Bernd Fischer
Guest
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| Posted:
Fri Sep 03, 2004 1:31 pm Post subject:
Re: Assura LVS questions: layout and schematic match but got |
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You have more than one net connected to one layer area 'nxwell',
means more than one net connected to the same NWell, I guess.
And the same for 'psub' which should be your p+ substrate.
Assura does not flag shorts over high resistive areas like wells
or substrate layers as short in the lvs report. Most of the time
the connection to these kind of layers are defined in your rules
with a geomStamp command, which then outputs these kind of error messages.
Look in your LVS run directory for a file <runName>.err there you
will find more details and coordinates for this errors.
Bernd
Jay Smith wrote:
| Quote: | Greetings,
I did a couple of Assura LVS checks lately. All of my layouts match
the schematics. However, among them, I got some "error messages" from
within the ELW. Seems these errors won't affect RCX run, but what
exactly do these messages (from the ELW) mean?
------------------------------------------------
nxwell_StampErrorMult
nxwell_StampErrorConnect
psub_term_StampErrorMult
psub_term_StampErrorConnect
psub_StampErrorMult
psub_StampErrorConnect
------------------------------------------------
Thanks a lot for your inputs!
Jay |
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Jay Lessert
Guest
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| Posted:
Fri Sep 03, 2004 6:57 pm Post subject:
Re: Assura LVS questions: layout and schematic match but got |
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mail9900@yahoo.com (Jay Smith) wrote in message news:<35c9712a.0409022138.47be20b5@posting.google.com>...
| Quote: | within the ELW. Seems these errors won't affect RCX run, but what
exactly do these messages (from the ELW) mean?
------------------------------------------------
nxwell_StampErrorMult
nxwell_StampErrorConnect
psub_term_StampErrorMult
psub_term_StampErrorConnect
psub_StampErrorMult
psub_StampErrorConnect
|
Floating taps. Substrate or Nwell taps that do not have a
hard-wired path to ground or power (or if you have multiple
power/ground nodes, possibly a short through well or substrate.
You see they come in pairs; IIRC, one of the two shows
you explicitly which set of taps (could be only one)
is in the minority of the node conflict.
-Jay- |
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Jay Smith
Guest
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| Posted:
Mon Sep 06, 2004 9:27 am Post subject:
Re: Assura LVS questions: layout and schematic match but got |
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Thanks all for you reply.
I don't have any floating p-sub or nwell taps. As for Bernd
's comment, I do have multiple nwell connected to the same net - which
is vdd!. Same for the p-sub body contact. In my circuit, all nmos bulk
nodes are connected to ground, and all pmos bulk nodes are connected
to power supply.
What I did is I made a lot of p-sub and nwell taps. Those contacts are
connected together through metal 1. Then I'm running 4 long global
wires (metal 3) for vdd! and gnd!, and I connected those taps to these
4 wires. I didn't see anythng wroing here... Please advise.
thanks again,
Jay |
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Jay Lessert
Guest
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| Posted:
Wed Sep 08, 2004 11:42 pm Post subject:
Re: Assura LVS questions: layout and schematic match but got |
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mail9900@yahoo.com (Jay Smith) wrote in message news:<35c9712a.0409052127.59b529cb@posting.google.com>...
| Quote: | Thanks all for you reply.
I don't have any floating p-sub or nwell taps.
|
Yes, you do. "Floating" may not be exactly the right
word, but it is the customary description in the trade.
In your extract code, you've got something like:
geomStamp( psub ptie error )
The Assura Command Reference (assuracommandref.pdf) has a
complete (if somewhat confusing until you read it 3-4 times)
description of geomStamp() error output. You're seeing
psub_StampErrorMult (all psub geometries that are touched
by ptie geometries having more than one netname) and
psub_StampErrorConnect (the subset of ptie geometries that
are in the MINORITY of ptie's with different netnames).
If you look at the StampErrorMult output, you'll see something
different about those particular ties. Also check your .erc
output for texting problems.
-Jay- |
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Ethan Dawe
Guest
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| Posted:
Sun Sep 26, 2004 4:12 am Post subject:
Re: Assura LVS questions: layout and schematic match but got |
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You may also be missing an nwell layer around a pmos device. Sometimes in
custom layouts (and in some pcells) you can turn on/off the nwell drawing
and insert one manually. I suggest you turn off all layes but p+ n+ and
nwell and look for a n+ well tie that is outside the well. Barring that I
would highlight your ground and supply nodes individually and look for one
that isn't tied properly. Any floating nwell ties will show as an additional
"stamp" of the nwell and floating psub ties will be "soft" connected to
other psub ties. Since they are not directly ties to improper nets, they are
floating, or at best soft connected.
Ethan
"Jay Lessert" <jayl-news@accelerant.net> wrote in message
news:7109f92b.0409081142.47c3e77b@posting.google.com...
| Quote: | mail9900@yahoo.com (Jay Smith) wrote in message
news:<35c9712a.0409052127.59b529cb@posting.google.com>...
Thanks all for you reply.
I don't have any floating p-sub or nwell taps.
Yes, you do. "Floating" may not be exactly the right
word, but it is the customary description in the trade.
In your extract code, you've got something like:
geomStamp( psub ptie error )
The Assura Command Reference (assuracommandref.pdf) has a
complete (if somewhat confusing until you read it 3-4 times)
description of geomStamp() error output. You're seeing
psub_StampErrorMult (all psub geometries that are touched
by ptie geometries having more than one netname) and
psub_StampErrorConnect (the subset of ptie geometries that
are in the MINORITY of ptie's with different netnames).
If you look at the StampErrorMult output, you'll see something
different about those particular ties. Also check your .erc
output for texting problems.
-Jay- |
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