DrunkBear
Joined: 06 Jun 2007
Posts: 1
|
 Posted:
Wed Jun 06, 2007 10:52 am Post subject:
VHDL toolbox questions |
|
|
Dear masters, I spent a lot of time studing Cadence references and havn't found answers for lot of questions. Here is some of them:
1. Is it possible to create vhdl or verilog model from existing multylevel schematic project? (for example, by writing vhdl/verilog code for basic components and generating pure digital model)
2. After starting vhdl toolbox from CIW and succesfull hierarchy check and elaboration simuton still not starts(withoughtanny comments in cosole and log). Can anybody explain what's the problem?
3. Is there any GUI for design of input sequences for simulation of digital models?
|
|
FAQ
Memberlist
Register
Profile
Log in to check your private messages
Log in
