aprior
Joined: 06 Apr 2006
Posts: 1
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 Posted:
Thu Apr 06, 2006 5:15 pm Post subject:
Verilog simulation: Can't descend into cell views |
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-- Problem solved see below --
I am having a problem trying to simulate with a verilog-a file. The schematic sims just fine until I use the hierachy editor to switch in a verilog-a view. I get the error:
ERROR: Netlister: unable to descend into any of the views defined in the view list: "veriloga" for instance I14 in cell SigmaDelta_sim. Either add one of these views to: Library: ap_lib Cell: firstorder_sigmadelta or modify the view list to contain an existing view.
I have the following hierarchy settings:
Library list: ap_sim ap_lib
View List: spectre cmos_sch schematic veriloga ahdl
Stop List: spectre veriloga
-- Solved --
The VI editor normally comes up, but I use another editor, that doesn't give me an indication that it passed the parser. Using the VI editor for all changes gives me the passed syntax (parser) check message. Everything seems to be working fine now.
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