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tarekmh
Joined: 22 Mar 2005
Posts: 8
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 Posted:
Mon Dec 26, 2005 9:51 am Post subject:
tsmc 0.18u pdk cdl lvs |
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Hi,
I am using the tsmc 0.18u pdk on cadence env. I am trying to make an lvs, it was stated that I need to make a cdl to gds comparison for a complete lvs not a dfII lvs (schematic versus layout). I am using assura 3.14 and cadence 5.14 versions. Can anybody help me with that.
Regards
Tarek
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DReynolds
Joined: 24 Mar 2005
Posts: 16
Location: Scarborough ME
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Tue Jan 03, 2006 3:17 pm Post subject:
Assura lvs on tsmc 0.18u |
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Tarek, can you please provide a bit more info... why do you think you need to go to gds to do lvs? IYou can run drc and lvs right from the virtuoso menus... have you been able to run any kind of verification? If you know that your path ito the Assura files is good, you stream out and cdl out to get your files, then just edit the rsf to point to the gds and cdl rather than the db files and it should work fine.
David |
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tarekmh
Joined: 22 Mar 2005
Posts: 8
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Tue Jan 03, 2006 3:46 pm Post subject:
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Hi David,
I have solved the problem I had, it concerns the transistor binding "bind.rul"
Thanks
Tarek
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