Andrew Beckett
Guest
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 Posted:
Tue Nov 29, 2005 5:10 pm Post subject:
Re: VHDL test bench (Cadence problem) |
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On 21 Nov 2005 12:55:44 -0800, "Vitaliy" <raven_007g@hotmail.com> wrote:
| Quote: | Hi,
I'm trying to simulate this in Cadence:
http://www.csee.umbc.edu/help/VHDL/samples/bmul32.vhdl
I don't have any problems with that,I can compile the files using
"ncvhdl -v93". I can also import the files in Synopsis and get gate
level as expected.
However, when I try to compile
http://www.csee.umbc.edu/help/VHDL/samples/bmul32_test.vhdl
I get this error.
ncvhdl: 05.10-p004: (c) 1995-2003 Cadence Design Systems, Inc.
ncvhdl_p: *internal* (expecting FUNCTION of PROCEDURE).
Please contact Cadence Design Systems about this problem and provide
enough information to help us reproduce is it.
I'm really stuck on this. Any help would be much appreciated.
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I tried compiling these with IUS55 - and once I'd commented out the add32 and
fadd instances (since I didn't have definitions for these), both compiled and
then elaborated OK.
So perhaps you just need to use a newer version. I didn't have a chance to test
with LDV51.
Regards,
Andrew. |
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