trisha.woods
Guest
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 Posted:
Thu Nov 03, 2005 1:10 am Post subject:
Report Sensitized Path |
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Hi,
Is there any tool (preferably within cadence) that can report the
nets, cells and pins involved in path undergoing a logic transistion.
For example, I have a gate netlist and a input vector sequence ( e.g.
1110->1111 i.e. transition on LSB ) and I want to know all the gates,
nets and pins through which the logic transition propagates from input
(LSB) to the output (or outputs).
Regards
Trisha.
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Heidi
Guest
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| Posted:
Sun Nov 06, 2005 7:51 am Post subject:
Re: Report Sensitized Path |
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You can try GOF, Gates-On-the-Fly. A graphical tool to handle netlist.
The powerful partial schematic feature is very useful in debug netlist
and report the related nets, cells and pins in your case.
Find one cell that LSB connecting to, bring up GofTrace(netlist trace
and debug tool) with the cell, click on the output pin of the cell, the
fanout cells will appear on GUI window. And keep on clicking and
tracing, a circuit will be created.
Goto www.nandigits.com and download for free trial.
Let me know if you have any problem.
Heidi
trisha.woods wrote:
| Quote: | Hi,
Is there any tool (preferably within cadence) that can report the
nets, cells and pins involved in path undergoing a logic transistion.
For example, I have a gate netlist and a input vector sequence ( e.g.
1110->1111 i.e. transition on LSB ) and I want to know all the gates,
nets and pins through which the logic transition propagates from input
(LSB) to the output (or outputs).
Regards
Trisha. |
|
|
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