Cadence
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CADForums.net Forum Index -> Cadence 

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No new posts How extract results (mu/sd) from histogram of MonteCarlo A
1 cadence Tue Mar 09, 2010 9:10 pm
CarlB
No new posts How to find process parameters
0 nttnrvr Sun Feb 14, 2010 1:05 pm
nttnrvr
No new posts how to use PTM module files in HSPICE (windows version 2009)
0 nanochipware Fri Dec 11, 2009 12:22 pm
nanochipware
No new posts Assura DRC Error
0 simopoulos Thu Oct 29, 2009 11:21 am
simopoulos
No new posts Diva LVS, parallel of 3 or more Transistors
0 GerhardGaupp Thu Oct 08, 2009 11:52 am
GerhardGaupp
No new posts back annotate vdsat, id, gm, etc
0 dhruv7126 Thu Aug 27, 2009 11:43 pm
dhruv7126
No new posts assura extraction and calibre extraction
0 deepak242003 Mon Jul 27, 2009 9:04 am
deepak242003
No new posts fprintf/sprintf: format spec:incompatible with data - nil
0 cl254 Sat Jun 20, 2009 7:51 pm
cl254
No new posts Cannot plot current: ..does not evaluate to an object that..
0 cl254 Sat Jun 20, 2009 7:22 pm
cl254
No new posts ahdlcmi related fail in IC610 spectre sim
0 ams123 Sun May 10, 2009 4:45 pm
ams123
No new posts assura extraction of an inductor
0 chacha Wed May 06, 2009 10:39 am
chacha
No new posts Assura script question
0 saad Tue Apr 28, 2009 1:40 pm
saad
No new posts PDK change , from 0.18um to 01.3um
0 mitgrace Fri Apr 24, 2009 8:41 am
mitgrace
No new posts about edif out in cadence
0 zzx19831119 Wed Mar 11, 2009 11:27 am
zzx19831119
No new posts changing pathWidth while using "enterPath" functio
0 sudha Thu Feb 05, 2009 1:02 pm
sudha
No new posts ic 5141 on redhat AS 4
1 asueee Wed Dec 24, 2008 11:29 am
ninge
No new posts how to give trailing edge ramp waveform in cadence spectre
0 kvk113 Fri Nov 21, 2008 11:08 am
kvk113
No new posts how to use leSearchHierarchy when criteria is user property
0 aiou Tue Sep 09, 2008 5:16 am
aiou
No new posts Why won't schPlot() work here?
7 leddedup Fri Aug 01, 2008 2:56 am
Saroj
No new posts segmentation fault
0 firsttimedesigning Tue Feb 26, 2008 9:53 am
firsttimedesigning
No new posts Export CDL netlist
0 seijihiko Thu Jun 28, 2007 7:17 am
seijihiko
No new posts VHDL toolbox questions
0 DrunkBear Wed Jun 06, 2007 10:52 am
DrunkBear
No new posts Jump to XY coordinates
0 vikaskm Wed May 23, 2007 8:09 am
vikaskm
No new posts I'm new member, and need help!! I need quick SKILL tutorial
1 ahmad_abdulghany Wed Apr 11, 2007 3:52 am
microhdl
No new posts Simulating Spice Netlists
3 nabil Mon Jan 01, 2007 6:32 pm
thly99
No new posts plotStyle() isn' valid for Wavescan.
0 pancho_hideboo Sat Nov 18, 2006 4:15 pm
pancho_hideboo
No new posts problem with mixed-signal simulation
1 xiaolong Thu Nov 02, 2006 1:21 am
thly99
No new posts capgen Assura
0 leo47 Wed Sep 27, 2006 12:36 pm
leo47
No new posts monte carlo simulation
0 leo47 Tue Sep 26, 2006 8:22 am
leo47
No new posts what's wrong with the function ocnYvsYplot?
0 wjx197733 Fri Jun 30, 2006 12:56 pm
wjx197733
No new posts How to use Layer Boolean Functions with hierarchical objects
0 yujie29 Thu Apr 27, 2006 5:45 pm
yujie29
No new posts Calibre in Cadence
0 elbadry Thu Apr 27, 2006 12:49 pm
elbadry
No new posts cross cursor in virtuoso layout editor
0 eng_semi Wed Apr 26, 2006 4:01 pm
eng_semi
No new posts Virtuoso help urgent
0 p_shinde Wed Apr 26, 2006 1:08 pm
p_shinde
No new posts About lambda function defined in PCell
0 Thomas Sat Apr 15, 2006 4:43 am
Thomas
No new posts Verilog simulation: Can't descend into cell views
0 aprior Thu Apr 06, 2006 5:15 pm
aprior
No new posts Retrieving instance parameter values
0 castrolopez Thu Apr 06, 2006 3:52 pm
castrolopez
No new posts Suggestion to saving states in analog artist
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21 Svenn Are Bjerkem Sat Mar 04, 2006 9:52 pm
tykim
No new posts about swaping and chips.prt
0 chekunidze Thu Feb 09, 2006 7:57 am
chekunidze
No new posts question about analog artist
0 arsenal Wed Feb 01, 2006 10:39 pm
arsenal
No new posts VerilogA Parameter - string?
0 hikom Tue Jan 24, 2006 12:15 pm
hikom
No new posts Problems by Simulation with Virtuoso Analog Design Envirnome
3 Andre Tue Jan 24, 2006 10:59 am
hikom
No new posts troubles with the diva Design Rule Check
0 Andre Thu Jan 05, 2006 4:51 pm
Andre
No new posts tsmc process survey
0 tarekmh Wed Jan 04, 2006 11:13 am
tarekmh
No new posts tsmc 0.18u pdk cdl lvs
2 tarekmh Tue Jan 03, 2006 3:46 pm
tarekmh
No new posts Calibre 2003.2
0 020170 Sat Dec 31, 2005 11:35 am
020170
No new posts What is SKILL?
0 020170 Sat Dec 31, 2005 11:30 am
020170
No new posts plm library path...
0 sri_1983 Wed Dec 28, 2005 8:02 am
sri_1983
No new posts versions of cadence tools
5 ahmad Wed Dec 21, 2005 12:57 pm
hikom
No new posts cadence layout into Hspice netlist conversion
0 020170 Sun Dec 18, 2005 10:06 am
020170
 
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